1. Field of the Invention
This invention relates to a synchronous semiconductor device. More particularly, this invention relates to a synchronous semiconductor memory device which is provided with dynamic memory cells requiring the refresh operation and is operated in synchronism with an external clock signal and an operating method thereof. For example, this invention can be applied to a fast cycle synchronous DRAM (SDR-FCRAM), double data rate synchronous DRAM (DDR-FCRAM) having the data transfer rate which is twice that of the former device and the like.
2. Description of the Related Art
In the conventional SDRAM (Synchronous Dynamic Random Access Memory), the memory cell array is divided into a plurality of banks and successively performs the data read/write operations in synchronism with a clock signal from the exterior while switching the banks. In recent years, a memory which is designed to attain the high-speed data rate, for example, a double data rate DDR-SDRAM designed to achieve the data transfer rate which is twice that of the above device becomes dominant. However, in an application in which random cycle time is important as in a network system or the like, it is necessary to enhance the operation speed of the bank itself.
The above problem can be solved by use of the DDR-FCRAM (Fast Cycle Random Access Memory). Like the DDR-SDRAM, in the DDR-FCRAM, the memory cell array is divided into a plurality of banks. In this case, the data read/write operations can be successively performed in synchronism with an external clock signal and data can be transferred at high speed of double data rate. In addition to the above feature, random cycle time can be shortened by improving the operation of accessing to the memory cell array and using a new write system. Therefore, the device has received much attention in the application of the network system or the like. However, the DRAM cell requires the refresh operation. Therefore, in order to further enhance the application efficiency of the bus in the entire system, it becomes important to shorten the refresh cycle time and reduce disturb time due to the refresh operation.
Next, the operation of the FCRAM is schematically explained with reference to FIGS. 1, 2A, 2B and 3. FIG. 1 is a state transition diagram of the FCRAM, FIGS. 2A and 2B are command tables and FIG. 3 is a timing chart of each command. As shown in FIGS. 2A, 2B and 3, the command system of the FCRAM is set up by a combination of a first command and a second command. The command is controlled according to the levels of two pins including a chip select pin (chip select signal /CS) and a function pin (function signal FN). Thus, a large number of commands can be determined by use of a small number of control pins by determining a command according to a combination of the levels of the control pins (chip select pin and function pin) at input timing of the first command and the levels of the above control pins at input timing of the second command.
As shown in the command table of FIG. 2A, for example, the first command is a read active command RDA and write active command WRA. As shown in the command table of FIG. 2B, the second command is a lower address latch command LAL, auto-refresh command REF and mode register command MRS.
As shown in the state transition diagram of FIG. 1, for example, the read operation (READ) is performed as follows. In the standby state (STANDBY), first, the chip select signal /CS is set to the “L” level and the function signal is set to the “H” level at the input timing of the first command to set a read active command RDA (Read with Auto-close). Then, an upper address UA used to select a column and a bank address BA used to select a bank are input. Next, the chip select signal /CS is set to the “H” level at the input timing of the second command one clock (tCK) after the input timing of the first command. Then, a column address latch command LAL (Lower Address Latch) which latches a row address is set and a lower address LA which selects a row is input. After this, the state is automatically returned to the standby state and the read operation is terminated.
The write operation (WRITE) is performed by setting a write active command WRA (Write with Auto-close) in which only the logical level of the function signal FN is different in comparison with that used in the case of the read operation as the first command and inputting an upper address UA and bank address BA. Then, a column address latch command LAL is set by setting the chip select signal /CS to the “H” level at the input timing of the second command one clock after the input timing of the first command and a lower address LA is input. After this, the state is automatically returned to the standby state and the write operation is terminated.
In the operation of the FCRAM internal portion, as shown in the block diagram of FIG. 4, an internal command decoder 100 detects the read operation and supplies a detection signal to a control logic 101 when a read active command RDA is received at the input timing of the first command. The control logic 101 determines the operation timing of the internal circuit according to information such as latency of the write/read operation from a mode register 102 and outputs a control signal CS. A bank address and upper address received at this time are fetched by an address receiver 103 which logically converts the received address levels. Then, an upper address latch 104 is controlled by the control signal CS output from the control logic 101 to select one of banks A, B, C, D, . . . and a word line WL and read out cell data. After the cell data is read out, the operation of transferring charges (information) written into the cell to the bit line and amplifying the data by use of a bit line sense amplifier is performed.
When a lower address latch command LAL is received as the second command, a lower address LA which is a column address received at this time is logically converted by the address receiver 103 and a lower address output therefrom is latched by a lower address latch 105 which in turn generates an internal Y address. Further, a column decoder 106 selects a column selection line CSL to transfer data on the bit line to a data line. Then, data is logically determined by a second sense amplifier 107 and temporarily held in a data latch control 108. A burst counter 109 and sync. circuit 110 are used to control output timing of burst data and operation timing of an output buffer (input/output buffer 111) and data is output to the exterior according to the read latency.
In this case, since the DRAM cell is a destructive read type cell, the charge is rewritten into the cell by use of the bit line sense amplifier even after the column select line CSL is set into the non-selected state. After this, the word line WL is reset by use of a bank timer which controls the operation of the bank set in the internal portion, the operation is automatically returned to the bit line precharge operation and the state is set to the standby state.
As to the FCRAM write operation, the applicant of this invention proposed a data write system of “Delayed Write” system (which is hereinafter referred to as a Late Write system) in “Semiconductor Memory Device” of Jpn. Pat. Appln. KOKAI Publication No. P2000-137983. In the data write system, a system of temporarily holding a received address and write data and writing data into a cell in a next cycle by use of the address and write data received in the preceding cycle is used in order to shorten random cycle time tRC. Thus, the random cycle time is shortened. If the late write system is not used, it is necessary to operate the column select line CSL and perform the write operation with respect to the cell after receiving write data of one burst and it becomes impossible to shorten the random cycle time tRC.
Next, the internal operation in the write cycle of the FCRAM is explained. When a write active command WRA is received as the first command, the command decoder 100 detects the write operation and outputs a detection signal to the control logic 101. The control logic 101 determines the operation timing of the internal circuit according to information such as write/read latency from the mode register 102 and issues a control signal CS. Further, a bank address BA and upper address UA supplied at this time are fetched and the levels of the fetched addresses are logically converted by the address receiver 103. Then, the upper address latch 104 temporarily holds the logically converted address and outputs upper address information held in the preceding write cycle as an internal X address to select one of the banks A, B, C, D, . . . and a word line WL.
When a column address latch command LAL is received as the second command, a lower address LA which is a column address supplied at this time is logically converted by the address receiver 103. Then, the lower address is temporarily held in the lower address latch 105 which in turn outputs a lower address LA held in the preceding write cycle as an internal Y address to the column decoder 106. Thus, the column decoder 106 selects a column select line CSL. Further, the operation of temporarily holding write data received by the data latch control section 108 and the operation of writing data into the cell are performed. The operation of writing data into the cell is performed by outputting write data held in the preceding write cycle to the data line, supplying the data to the bit line via the column select line CSL and writing the data into the cell by use of the bit line sense amplifier. After this, the word line WL is reset by use of the bank timer set in the internal portion and the operation is automatically returned to the bit line precharge operation.
As described above, the late write system is to temporarily hold an address and write data received in the write cycle in the latch circuit section and perform the write operation into the cell in a next cycle by use of the thus held address and write data. As a result, the random cycle time can be shortened.
So far, the read or write operation in which the first command is the read active command RDA or write active command WRA and the second command is the lower address latch command LAL has been described.
However, as described above, in a case where the chip select signal /CS is set at the “L” level, an auto-refresh command REF and mode register command MRS are provided as the second command other than the lower address latch command LAL. Since the mode register command MRS is not directly associated with the present invention, the detail explanation thereof is omitted and the auto-refresh command REF which is directly associated with the present invention is explained in detail.
As shown in the command table of FIG. 5A, the auto-refresh operation (AUTO-REFRESH) can be performed when the write active command WRA which is used as the first command and the auto-refresh command REF which is used as the second command are combined. That is, the auto-refresh operation can be performed by inputting the write active command WRA as the first command like the case of the write operation and the auto-refresh command REF which is different from the case of the write operation as the second command. In this case, since the write active command WRA is input in each case of the write operation and the auto-refresh operation as the first command, it is impossible to determine whether the operation is the write operation or the auto-refresh operation simply by receiving the first command. Further, if the write operation is started after the second command is received, start of the operation is delayed by one cycle so that shortening of the random cycle time which is the feature of the FCRAM will be obstructed. Therefore, in order not to obstruct shortening of the random cycle time, the system is designed to first perform the write operation even in the auto-refresh operation and then start the actual auto-refresh operation after the end of the above write operation.
Next, the auto-refresh operation is explained with reference to the timing chart of FIG. 6. FIG. 6 is a timing chart in a case where the auto-refresh operation is performed after the write operation and a case wherein the read latency CL is “4” and the burst length BL is “4” is shown as an example. First, in order to enter into the write operation, a write active command WRA, bank address BA and upper address UA are input as the first command at the timing at which an external clock signal is set at “0”. Then, a lower address latch command LAL and lower address LA are input as the second command at timing one clock after the above timing. Since the write latency is equal to “(read latency) −1”, the input timing of write data is so set that data items D0 to D3 with the burst length of “4” will be input at the double data rate in synchronism with both of the leading and trailing edges of the external clock signal three cycles after input of the second command.
As described above, in the write operation of the FCRAM, the received address and write data are temporarily held in the internal latch circuit section. In the write operation, the late write operation of writing data into the cell by use of the address and write data which are actually received in the preceding cycle and temporarily held in the latch circuit section is performed. That is, a word line WLa and column select line CSa are selected by use of the address received in the preceding write operation and the late write operation of writing write data received in the write operation in the preceding cycle into the cell selected by the above lines is performed. After this, the word line WL is reset by use of the bank timer set in the internal portion, the operation is automatically returned to the bit line precharge operation and the state is set to the standby state.
In the above example, the random cycle time tRC is set equal to five clocks of the clock cycle time tCK. Since it is permitted to input the auto-refresh command after lapse of the random cycle time tRC, the write active command WRA is input at timing at which five clocks of the external clock signal have elapsed and the auto-refresh command REF is input when next one clock has elapsed.
As described before, in the conventional FCRAM, the write operation is first performed even in the auto-refresh operation. Then, the late write operation of an address and write data received in the write operation in the preceding cycle is first performed in the auto-refresh operation. A word line WLb and column select line CSLb are selected in the write operation. After this, the word line WL is automatically reset by use of the bank timer, the operation is automatically returned to the bit line precharge operation and the write operation is terminated. Next, a word line WLc is selected by use of a refresh address counter which counts up for each refresh operation. Then, the refresh operation period is controlled by a refresh timer which controls the refresh operation period and the state is automatically returned to the standby state.
The operation enters into the self-refresh operation (SELF-REFRESH) shown in FIG. 5B by inputting the same auto-refresh command REF as the second command in the auto-refresh operation and setting a power down signal /PD to the “L” level. The self-refresh operation basically follows after the auto-refresh operation and automatically continues the refresh operation according to the period of a self-refresh timer set in the internal portion.
As described before, auto-refresh cycle time tREFC as viewed from the exterior is determined by the sum of the first late write operation time and the actual refresh operation time. Therefore, the auto-refresh cycle time tREFC in the conventional FCRAM becomes longer by the time of the late write operation.
In the auto-refresh command system in the conventional synchronous semiconductor memory device and the operating method thereof, the first command (write active command WRA) which is the same as that used in the write operation is used and the second command (auto-refresh command REF) which is different from that used in the write operation is input. Therefore, since the write active command WRA is input as the first command in both cases of the write operation and auto-refresh operation, it is impossible to determine whether the operation is the write operation or the auto-refresh operation simply by receiving the first command.
Thus, in the auto-refresh operation, the refresh operation is performed after the write operation is first performed and there occurs a problem that shortening of the auto-refresh cycle time is obstructed.
Further, if the write operation is started after the second command is received, start of the operation is delayed by one cycle and there occurs a problem that shortening of the random cycle time which is the feature of the FCRAM is obstructed.